Fabrication process of semiconductor package and semiconductor package

ABSTRACT

A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

TECHNICAL FIELD

[0001] This invention relates to a process for the fabrication of asemiconductor package and also to a semiconductor package.

BACKGROUND ART

[0002] As the level of integration of semiconductors becomes higher, thenumber of input/output terminals increases. A need has therefore arisenfor a semiconductor package having many input/output terminals. Ingeneral, input/output terminals can be divided into two types, one beingthose arranged in a single row along a periphery of a package and theother being those arranged in multiple arrays not only along a peripheryof a package but also inside the package. The former is typified by QFPs(Quad Flat Packages). To provide them with many terminals, it isnecessary to reduce the pitch of the the terminals. In a pitch range of0.5 mm and shorter, an advanced technique is required for theirconnection with a printed board. The latter array type permits arrangingterminals at a relatively large pitch and is hence suited for a high pincount.

[0003] Among such array types, PGAs (Pin Grid Array) which are providedwith connecting pins have heretofore been commonly used. However, theirconnections with printed boards are conducted by insertion, so that theyare not suited for surface mounting. To overcome this inconvenience,packages called BGAs (Ball Grid Arrays) which permit surface mountinghave been developed. These BGAs can be classified into (1) the ceramictype, (2) the printed wiring board type and (3) the tape type making useof TAB (tape automated bonding). Of these, the ceramic type has ashorter distance between a mother board and a package compared with theconventional PGAs so that a warp in the package due to a difference inthermal stress between the mother board and the package remains aserious problem. Further, the printed wiring board type is alsoaccompanied by problems such as substrate warping, low moistureresistance, low reliability and large substrate thickness. Tape BGAsmaking use of the TAB technology have therefore been proposed.

[0004] With a view to meeting a further reduction in the package size,packages having substantially the same size as semiconductor chips,namely, so-called chip size packages (CSP) have been proposed. Each ofthem has connecting portions, which are to be connected with an externalprinted board, in a mounting area rather than at a peripheral portion ofa semiconductor chip.

[0005] Specific examples of such CSPs include those fabricated bybonding a bumped polyimide film to a surface of a semiconductor chip,establishing electrical connection with the chip and gold lead wires,and potting an epoxy resin or the like to seal the resultant package(NIKKEI MATERIALS & TECHNOLOGY, No. 140, pp.18-19, April, 1994) andthose obtained by forming metal bumps on a temporary substrate atpositions corresponding to points of connection between a semiconductorchip and an external printed board, bonding the semiconductor chipfacedown, and subjecting it to transfer molding on the temporarysubstrate (Smallest Flip-Chip-Like Package CSP; The Second VLSIPackaging Workshop of Japan, pp.46-50, 1994).

[0006] On the other hand, packages making use of a polyimide tape as abase film are studied in the fields of BGAs and CSPs as mentioned above.In this case, as the polyimide tape, one having a copper foil laminatedon a polyimide film via an adhesive layer is commonly employed. However,from the viewpoint of heat resistance and moisture resistance, onehaving a polyimide layer formed directly on a copper foil, that is, aso-called two-layer flexible base material, is preferred. Productionprocesses of such two-layer flexible base materials are roughly dividedinto (1) a process in which polyamic acid as a precursor for a polyimideis coated on a copper foil and is then hardened and (2) a process inwhich a thin metal film is formed on a hardened polyimide film by vacuumdeposition or electroless plating. To provide, for example, holesreaching the copper foil by removing the polyimide at desired portions(which correspond to portions capable of exhibiting a second connectingfunction) while applying laser beam machining, it is preferred to makethe polyimide film as thin as possible. In contrast, upon forming atwo-layer flexible base material into the form of a leadframe andhandling the same, a base film of a small thickness involves problemssuch as low handling readiness and insufficient rigidity as a frame.

[0007] As has been described above, various proposals have been made assemiconductor packages capable of meeting miniaturization and highintegration. Nevertheless, further improvements are desired to providesatisfaction in all aspects such as performance, characteristics andproductivity.

[0008] An object of the present invention is to provide a process forthe fabrication of a semiconductor package, the process making itpossible to stably fabricate with good productivity semiconductorpackages capable of meeting miniaturization and high integration, andalso to provide such a semiconductor package.

DISCLOSURE OF THE INVENTION

[0009] In a first aspect of the present invention, there is thusprovided a process for the fabrication of a semiconductor package, whichcomprises the following steps:

[0010] 1A) forming wiring on one side of a conductive temporarysupporting member;

[0011] 1B) mounting a semiconductor device on the conductive temporarysupporting member on which the wiring has been formed, and thenelectrically connecting a terminal of the semiconductor device with thewiring;

[0012] 1C) sealing the semiconductor device with resin;

[0013] 1D) removing the conductive temporary supporting member to exposethe wiring;

[0014] 1E) forming an insulating layer over the exposed wiring at anarea other than a position where an external connection terminal is tobe formed; and

[0015] 1F) forming the external connection terminal on the wiring at thepositions where the insulating layer has not been formed.

[0016] In a second aspect of the present invention, there is alsoprovided a process for the fabrication of a semiconductor package, whichcomprises the following steps:

[0017] 2A) forming wiring on one side of a conductive temporarysupporting member;

[0018] 2B) forming an insulating supporting member over the one side ofthe conductive temporary supporting member, the one side carrying thewiring formed thereon;

[0019] 2C) removing the conductive temporary supporting member and thentransferring the wiring onto the insulating supporting member;

[0020] 2D) removing the insulating supporting member at positions wherean external connection terminal is to be formed for the wiring, wherebya through-holes is formed for the external connection terminal;

[0021] 2E) mounting a semiconductor device on the insulating supportingmember on which the wiring has been transferred, and then electricallyconnecting a terminal of the semiconductor device with the wiring;

[0022] 2G) sealing the semiconductor device with resin; and

[0023] 2H) forming, in the through-hole for the external connectionterminal, the external connection terminal so that the externalconnection terminal is electrically connected to the wiring.

[0024] In the second aspect of the invention, it is preferable toproceed from 2A to 2H; here, step 2D can come before 2B. For example,step 2B can be conducted by bonding an insulating film insulatingsupporting member previously provided with an external connectionterminal through-hole with one side of the conductive temporarysupporting member, the one side carrying the wiring pattern formedthereon.

[0025] In a third aspect of the present invention, there is alsoprovided a process for the fabrication of a semiconductor package, whichcomprises the following steps:

[0026] 3A) forming wiring on one side of a conductive temporarysupporting member;

[0027] 3B) mounting a semiconductor device on the conductive temporarysupporting member on which the wiring has been formed, and thenelectrically connecting a terminal of the semiconductor device with thewiring;

[0028] 3C) sealing the semiconductor device with resin;

[0029] 3D) removing the conductive temporary supporting member at anarea other than positions where an external connection terminal for thewiring is to be formed, whereby the external connection terminal madefrom the conductive temporary supporting member is formed; and

[0030] 3E) forming an insulating layer at the area other than theposition of the external connection terminal.

[0031] In a fourth aspect of the present invention, there is alsoprovided a process for the fabrication of a semiconductor package, whichcomprises the following steps:

[0032] 4A) forming a wiring on one side of a conductive temporarysupporting member;

[0033] 4B) mounting a semiconductor device on the conductive temporarysupporting member on which the wiring has been formed, and thenelectrically connecting a terminal of the semiconductor device with thewiring;

[0034] 4C) sealing the semiconductor device with resin;

[0035] 4D) forming a metal pattern, which is different in conditions forremoval from the conductive temporary supporting member, on another sideof the conductive temporary supporting member, the another side beingopposite to the one side where the semiconductor device has beenmounted, at a position where an external connection terminal for thewiring is to be formed; and

[0036] 4E) removing the conductive temporary supporting member at anarea other than the position where the metal pattern has been formed.

[0037] As a metal pattern, it is preferable to use solder. Further, goldlayer on nickel layer can be used.

[0038] In a fifth aspect of the present invention, there is alsoprovided a process for the fabrication of semiconductor packages, whichcomprises the following steps:

[0039] 5A) forming plural sets of wiring on one side of an insulatingsupporting member;

[0040] 5B) removing the insulating supporting member at positions whereexternal connection terminals for the wiring are to be formed, wherebythrough-holes for the external connection terminals are provided;

[0041] 5C) mounting semiconductor devices on the insulating supportingmember on which the plural sets of wiring have been formed, and thenelectrically connecting terminals of the semiconductor devices with thewiring, respectively;

[0042] 5D) sealing the semiconductor devices with resin;

[0043] 5E) forming, in the through-holes for the external connectionterminals, the external connection terminals so that the externalconnection terminals are electrically connected to the wiring; and

[0044] 5F) separating the resultant assembly into individualsemiconductor packages.

[0045] In the fifth aspect of the invention, it is preferable to proceedfrom 5A to 5F. However, 5A and 5B can be reversed. In other words, aplurality of sets of wiring can be formed on an insulating supportingmember provided with through-holes for external connection terminals.

[0046] In a sixth aspect of the present invention, there is alsoprovided a process for the fabrication of semiconductor packages, whichcomprises the following steps:

[0047] 6A) forming plural sets of wiring on one side of a conductivetemporary supporting member;

[0048] 6B) cutting apart the conductive temporary supporting member sothat the plural sets of wiring formed on the conductive temporarysupporting member are divided to include a predetermined number ofwiring per unit, and then fixing on a frame the separated conductivetemporary supporting member with the wiring formed thereon;

[0049] 6C) mounting semiconductor devices on the conductive temporarysupporting members on which the wiring has been formed, and thenelectrically connecting terminals of the semiconductor devices with thewiring, respectively;

[0050] 6D) sealing the semiconductor devices with resin;

[0051] 6E) removing the conductive temporary supporting member to exposethe wiring;

[0052] 6F) forming an insulating layer over the exposed wiring at areasother than positions where external connection terminals are to beformed;

[0053] 6G) forming the external connection terminals at the positionswhere the insulating layer for the wiring has not been formed; and

[0054] 6H) separating the resultant assembly into individualsemiconductor packages.

[0055] The predetermined number of wiring per unit in step 6B ispreferred to be one. However, in order to improve productivity, it canbe more than one.

[0056] In a seventh aspect of the present invention, there is alsoprovided a process for the fabrication of semiconductor packages, whichcomprises the following steps:

[0057] 7A) forming plural sets of wiring on one side of an insulatingsupporting member;

[0058] 7B) removing the insulating supporting member at positions whereexternal connection terminals for the wiring are to be formed, wherebythrough-holes for the external connection terminals are provided;

[0059] 7C) cutting apart the insulating supporting member so that theplural sets of wiring formed on the insulating supporting member aredivided to include a predetermined number of wiring per unit, and thenfixing on a frame the separated insulating supporting member with thewiring formed thereon;

[0060] 7D) mounting semiconductor devices on the insulating supportingmembers on which the wiring have been formed, and then electricallyconnecting terminals of the semiconductor devices with the wiring,respectively;

[0061] 7E) sealing the semiconductor devices with resin;

[0062] 7F) forming, in the through-holes for the external connectionterminals, the external connection terminals so that the externalconnection terminals are electrically connected to the wiring; and

[0063] 7G) separating the resultant assembly into individualsemiconductor packages.

[0064] In the fabrication process, it is preferable to proceed from 7Ato 7G. However, 7A and 7B can be reversed as in the fifth aspect of theinvention.

[0065] In an eighth aspect of the present invention, there is alsoprovided a process for the fabrication of a semiconductor packageprovided with a single layer of wiring, one side of the wiring having afirst connecting function of being connected with a semiconductor deviceand an opposite side of the wiring having a second connecting functionof being to be connected to external wiring, which comprises thefollowing steps 8A, 8B, 8C and 8D:

[0066] 8A) working a heat-resistant insulating base material having ametal foil, thereby forming the metal foil into plural sets of wiringpatterns;

[0067] 8B) forming a hole at a position for exhibiting the secondconnecting function which is to be formed in a subsequent step, so thatthe hole extends from a side of the insulating base material to thewiring patterns;

[0068] 8C) bonding a frame base material, which makes an opening througha predetermined portion thereof, to desired position on a surface of thewiring patterns and a surface of the insulating base material, thelatter surface being located adjacent the wiring patterns, respectively;and

[0069] 8D) mounting the semiconductor device, electrically connecting aterminal of the semiconductor device with the wiring pattern, and thensealing the semiconductor device with resin.

[0070] In the eight aspect of the invention, it is preferable to proceedfrom 8A to 8D. However, 8A and 8B can be reversed. In other words, metalfoil can be formed into wiring patterns after a hole is formed on theinsulating base material to extend to the metal foil.

[0071] In a ninth aspect of the present invention, there is alsoprovided a process for the fabrication of semiconductor packagesprovided with a single layer of a wiring, one side of the wiring havinga first connecting function of being connected with a semiconductordevice and an opposite side of the wiring having a second connectingfunction of being to be connected to external wiring, which comprisesthe following steps 9A, 9B, 9C and 9D:

[0072] 9A) working a heat-resistant insulating base material having ametal foil, thereby forming the metal foil into plural sets of wiringpatterns;

[0073] 9B) forming a hole at a position for exhibiting the secondconnecting function which is to be formed in a subsequent step, so thatthe hole extends from a side of the insulating base material to thewiring patterns;

[0074] 9C) bonding a second insulating base material, which makes anopening through a predetermined portion thereof, to a desired positionon a surface of the wiring patterns and a surface of the insulating basematerial, the latter surface being located adjacent to the wiringpatterns, respectively, whereby an insulating supporting member isformed;

[0075] 9D) cutting apart the insulating supporting member so that theplural sets of wiring formed on the insulating supporting member aredivided to include a predetermined number of wiring per unit, and thenfixing on a frame the separated insulating supporting member with thewiring formed thereon; and

[0076] 9E) mounting the semiconductor device, electrically connecting aterminal of the semiconductor device with the wiring, and then sealingthe semiconductor device with resin.

[0077] In the ninth aspect of the invention, it is preferable to proceedfrom 9A to 9E. However, 9A and 9B can be reversed as in the eight aspectof the invention.

[0078] In a tenth aspect of the present invention, there is alsoprovided a process for the fabrication of semiconductor packages, whichcomprises the following steps:

[0079] 10A) forming plural sets of wiring on one side of a supportingmember;

[0080] 10B) mounting plural semiconductor devices on the supportingmember on which the wiring have been formed, and then electricallyconnecting terminals of the semiconductor devices with the wiring;

[0081] 10C) subjecting the plural sets of electrically-connectedsemiconductor device and wiring to gang sealing with resin;

[0082] 10D) removing desired portions of the supporting member to exposepredetermined portions of the wiring, and forming external connectionterminals so that the external connection terminals are electricallyconnected to the exposed wiring; and

[0083] 10E) separating the resultant assembly into individualsemiconductor packages.

[0084] Metal foil can be used as the supporting member, and wiringpatterns can be exposed by removing the supporting member after sealingwith resin.

[0085] Further, the supporting member can be an insulating basematerial, and nonthrough-holes reaching the wiring patterns can beformed by removing a predetermined section of an insulating basematerial after sealing with resin.

[0086] In an eleventh aspect of the present invention, there is alsoprovided a process for the fabrication of a semiconductor devicepackaging frame, the frame being provided with pluralsemiconductor-device-mounting portions, portions connecting the pluralsemiconductor-device-mounting portions, and a registration mark portion,which comprises the following steps:

[0087] (a) forming wiring for the semiconductor-device-mounting portionson a conductive temporary substrate,

[0088] (b) transferring the wiring onto a resin substrate, and

[0089] (c) etching off the conductive temporary substrate;

[0090] wherein upon etching off the conductive temporary substrate instep (c), the conductive temporary substrate partly remains to form someof the connecting portions.

[0091] In the present invention, usual semiconductor devices such as LSIchips or IC chips can be used as the semiconductor devices.

[0092] To electrically connect the terminal of the semiconductor devicewith the wiring, it is possible to use not only wire bonding but alsousual means such as a bump or an anisotropic conductive film.

[0093] In the present invention, a warp-free and deformation-freesemiconductor package can be fabricated by subjecting a hardened sealingresin to heat treatment after a semiconductor device is sealed withresin.

[0094] The heat treatment can be conducted preferably at a temperaturein a range of the glass transition point of the hardened sealing resin±20° C., because the hardened resin exhibits strongest plasticproperties in the range of the glass transition point of the hardenedsealing resin ±20° C., thereby facilitating elimination of residualstrain. If the temperature of the heat treatment is lower than the glasstransition point −20° C., the hardened resin becomes a glassy elasticsubstance so that relaxation effects tend to be lessened. If thetemperature is higher than the glass transition point +20° C., thehardened resin turns to a rubbery elastic substance so that effect ofstrain elimination also tend to be reduced.

[0095] A warp or deformation in the semiconductor package can be morecompletely eliminated by cooling the semiconductor package to roomtemperature at a temperature-lowering rate of 5° C./min or less afterthe semiconductor package is heat-treated at a temperature in thetemperature of the glass transition point of the hardened sealing resin±20° C.

[0096] It is preferred to conduct the heat-treatment and/or cooling stepwhile pressing upper and lower surfaces of the hardened sealing resin byrigid flat plates under forces that reduce a warp or deformation in thehardened sealing resin.

[0097] In the semiconductor package according to the present invention,the wiring, where it is a single-layer wiring, is designed so that oneside of the wiring has a first connecting function for permittingconnection with the semiconductor chip and an opposite side of thewiring has a second connecting function enabling connection to theexternal wiring.

[0098] For the external connection terminals which are to be connectedto the external wiring, solder bumps, gold bumps or the like canpreferably be used.

[0099] From the standpoint of high densification, it is preferred toarrange the external connection terminals on a side further inward thana position where terminals of the semiconductor device are electricallyconnected by wire bonding or the like (fan-in type). As is understoodfrom the foregoing, it is preferred from the standpoint of highdensification to arrange the external connection terminals in agrid-like pattern on a lower side on which the semiconductor device ismounted.

BRIEF DESCRIPTION OF THE DRAWINGS

[0100]FIG. 1 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0101]FIG. 2 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0102]FIG. 3 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0103]FIG. 4 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0104]FIG. 5 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0105]FIG. 6 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0106]FIG. 7 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0107]FIG. 8 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0108]FIG. 9 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0109]FIG. 10 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0110]FIG. 11 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0111]FIG. 12 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0112]FIG. 13 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0113]FIG. 14 is a plan view illustrating the process according to anembodiment of the present invention for the fabrication of thesemiconductor package;

[0114]FIG. 15 is a plan view illustrating the process according to anembodiment of the present invention for the fabrication of thesemiconductor package;

[0115]FIG. 16 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0116]FIG. 17 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0117]FIG. 18 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0118]FIG. 19 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0119]FIG. 20 is a cross-sectional view illustrating the processaccording to an embodiment of the present invention for the fabricationof the semiconductor package;

[0120]FIG. 21 is a cross-sectional view illustrating the processaccording to an embodiment of the present invention for the fabricationof the semiconductor package;

[0121]FIG. 22 is a cross-sectional view illustrating a process accordingto an embodiment of the present invention for the fabrication of asemiconductor package;

[0122]FIG. 23 is a plan view illustrating a process according to anembodiment of the present invention for the fabrication of asemiconductor package;

[0123]FIG. 24 is a cross-sectional view illustrating the processaccording to an embodiment of the present invention for the fabricationof the semiconductor package; and

[0124]FIG. 25 is a cross-sectional view illustrating the processaccording to an embodiment of the present invention for the fabricationof the semiconductor package.

BEST MODE FOR CARRYING OUT THE INVENTION

[0125] With reference to FIG. 1, a description will be given of thefirst embodiment of the present invention.

[0126] A nickel layer of 0.001 mm in thickness (not shown in FIG. 1) isplated on one side of an electrolytic copper foil 1 of 0.035 mm inthickness. Next, a photosensitive dry film resist (“PHOTEC HN340”, tradename; product of Hitachi Chemical Co., Ltd.) is laminated, exposed andthen developed, so that a plating resist for wiring pattern is formed.Subsequently, electrolytic copper plating is conducted in a coppersulfate bath. Applied further are a nickel plating to a thickness of0.003 mm or greater and a gold plating of 99.9% or higher purity to athickness of 0.0003 mm or greater. The plating resist is next strippedoff, whereby a wiring 2 is formed (FIG. 1a). On the copper foil 1 withthe wiring 2 formed thereon as described above, an LSI chip 3 is mounted(FIG. 1b). For bonding the LSI chip, a silver paste 4 for semiconductorsis used. Next, LSI terminals and the wiring 2 are connected by wirebonds 100 (FIG. 1c). The thus-formed assembly was loaded in a die fortransfer mold and sealed with a semiconductor-sealing epoxy resin(“CL-7700”, trade name; product of Hitachi Chemical Co., Ltd.) 5 (FIG.1d). Thereafter, only the copper foil 1 was dissolved away with analkali etchant to expose the nickel. The nickel layer is removed with anickel stripper having low copper-dissolving power so that the wiringportions were exposed (FIG. 1e). Then, a solder resist 6 was coated andpatterned in such a way that connecting terminal portions were exposed.Solder balls 7 were arranged at the exposed portions of the wiring andwere caused to fuse there (FIG. 1f). The wiring can be connected to anouter wiring via these solder balls 7.

[0127] Referring to FIG. 2, a description will be given of the secondembodiment of the present invention.

[0128] Following the procedures of FIG. 1, a copper foil 1 with a wiring2 was prepared (FIG. 2a). An LSI chip 3 is mounted. The LSI chip isprovided with gold bumps 8 at terminal portions. These gold bumps 8 andterminal portions of the wiring 2 are connected together bythermocompression (FIG. 2b). Next, a liquid epoxy resin 9 is filledunderneath the LSI chip and cured (FIG. 2c). The thus-formed assemblywas loaded in a die for transfer mold and sealed with asemiconductor-sealing epoxy resin (“CL-7700”, trade name; product ofHitachi Chemical Co., Ltd.) 10 (FIG. 2d). Thereafter, only the copperfoil 1 was dissolved away with an alkali etchant to expose the nickel.The nickel layer was removed with a nickel stripper having lowcopper-dissolving power so that the wiring portions were exposed (FIG.2e). Then, a solder resist 6 was coated and patterned in such a way thatconnecting terminal portions were exposed. Solder balls 7 were arrangedat the exposed portions of the wiring and were caused to fuse there(FIG. 2f). The wiring can be connected to an outer wiring via thesesolder balls 7.

[0129] With reference to FIG. 3, a description will be given of thethird embodiment of the present invention.

[0130] A nickel layer of 0.001 mm in thickness (not shown in FIG. 3) isplated on one side of an electrolytic copper foil 1 of 0.035 mm inthickness. Next, a photosensitive dry film resist (“PHOTEC HN340”, tradename; product of Hitachi Chemical Co., Ltd.) is laminated, exposed andthen developed, so that a plating resist for wiring pattern is formed.Subsequently, electrolytic copper plating is conducted in a coppersulfate bath, so that a first wiring 13 is formed. The plating resist isnext stripped off and the first wiring 13 is subjected at a surfacethereof to oxidation treatment and reduction treatment. Using a freshcopper foil and a polyimide-base bonding film (“AS2210”, trade name;product of Hitachi Chemical Co., Ltd.) 12 as a bonding resin, they arelaminated and bonded so that the wiring 13 is positioned inside. (Holesof 0.1 mm in diameter are formed through the copper foil 11 by aconventional photoetching process. By a panel plating process, innerwalls of the holes and the entire surface of the copper foil are platedwith copper.) The copper foil is formed into a second wiring 11 byphotoetching. The resin (the polyimide-base bonding film 12) is removedat an LSI-mounting portion by an excimer laser to expose terminalportions. The terminal portions are applied with a nickel plating to athickness of 0.003 mm or greater and further with a gold plating of99.9% or higher purity to a thickness of 0.0003 mm or greater (FIG. 3a).On the copper foil 1 with the two-layer wiring pattern formed thereon asdescribed above, an LSI chip is mounted. For bonding the LSI chip, asilver paste for semiconductors was used (FIG. 3b). Next, LSI terminalsand the wiring 13 are connected by wire bonds 100 (FIG. 3c). Thethus-formed assembly was loaded in a die for transfer mold and sealedwith a semiconductor-sealing epoxy resin (“GL-7700”, trade name; productof Hitachi Chemical Co., Ltd.) 5. Thereafter, only the copper foil 1 wasdissolved away with an alkali etchant to expose the nickel. The nickellayer was removed with a nickel stripper having low copper-dissolvingpower so that the wiring portions were exposed (FIG. 3e). Then, a solderresist 6 was coated and patterned in such a way that connecting terminalportions were exposed. Solder balls 7 were arranged at the exposedportions and were caused to fuse there (FIG. 3f). The wiring can beconnected to an outer wiring via these solder balls 7.

[0131] With reference to FIG. 4, a description will be given of thefourth embodiment of the present invention.

[0132] On an SUS (stainless steel) sheet 14 of 0.1 mm in thickness, aphotosensitive dry film resist (“PHOTEC HN340”, trade name; product ofHitachi Chemical Co., Ltd.) is laminated, exposed and then developed, sothat a plating resist for wiring pattern is formed. Subsequently,electrolytic copper plating is conducted in a copper sulfate bath.Applied further are a nickel plating to a thickness of 0.003 mm orgreater and a gold plating of 99.9% or higher purity to a thickness of0.0003 mm or greater. The plating resist is next stripped off, whereby awiring 2 is formed (FIG. 4a). On the SUS sheet 14 with the wiring 2formed thereon as described above, a semiconductor chip 103 is mounted(FIG. 4b). For bonding the semiconductor chip, a silver paste 4 forsemiconductors was used. Next, semiconductor terminals and the wiring 2are connected by wire bonds 100 (FIG. 4c). The thus-formed assembly wasloaded in a die for transfer mold and sealed with asemiconductor-sealing epoxy resin (“CL-7700”, trade name; product ofHitachi Chemical Co., Ltd.) 5 (FIG. 4d). Thereafter, the SUS sheet 14was mechanically stripped off to expose the wiring portion (FIG. 4e).Then, a solder resist 6 was coated and patterned in such a way thatconnecting terminal portions were exposed. Solder balls 7 were arrangedat the exposed portions of the wiring and were caused to fuse there(FIG. 4f). The wiring can be connected to an outer wiring via thesesolder balls 7.

[0133] With reference to FIG. 5, a description will be given of thefifth embodiment of the present invention.

[0134] On an electrolytic copper foil of 0.035 mm in thickness, aphotosensitive dry film resist (“PHOTEC HN340”, trade name; product ofHitachi Chemical Co., Ltd.) is laminated, exposed and then developed, sothat a plating resist for wiring pattern is formed. Subsequent toapplication of a pattern plating 15 of nickel, electrolytic copperplating is conducted in a copper sulfate bath. Applied further are anickel plating to a thickness of 0.003 mm or greater and a gold platingof 99.9% or higher purity to a thickness of 0.0003 mm or greater. Theplating resist is next stripped off, whereby a wiring 2 is formed (FIG.5a). On the copper foil 1 with the wiring 2 formed thereon as describedabove, a semiconductor chip 103 is mounted (FIG. 5b). For bonding thesemiconductor chip, a silver paste 4 for semiconductors was used. Next,semiconductor terminal portions and the wiring 2 are connected by wirebonds 100 (FIG. 5c). The thus-formed assembly was loaded in a die fortransfer mold and sealed with a semiconductor-sealing epoxy resin(“CL-7700”, trade name; product of Hitachi Chemical Co., Ltd.) 5 (FIG.5d). Thereafter, the copper foil 1 was dissolved away with an alkalietchant to expose the wiring portions of nickel (FIG. 5e). Then, asolder resist 6 was coated and patterned in such a way that connectingterminal portions were exposed. Solder balls 7 were arranged at theexposed portions of the wiring and were caused to fuse there (FIG. 5 f).The wiring can be connected to an outer wiring via these solder balls 7.

[0135] With reference to FIG. 6, a description will be given of thesixth embodiment of the present invention.

[0136] On an electrolytic copper foil 1 of 0.035 mm in thickness, aphotosensitive dry film resist (“PHOTEC HN340”, trade name; product ofHitachi Chemical Co., Ltd.) is laminated, exposed and then developed, sothat a plating resist for wiring pattern is formed. Applied further area gold plating of 99.9% or higher purity to a thickness of 0.0003 mm orgreater and a nickel plating to a thickness of 0.003 mm or greater.Further, electrolytic copper plating is conducted in a copper sulfatebath, and the plating resist is stripped off, whereby a wiring 2 isformed (FIG. 6a). To the wiring-formed surface of the copper foil 1 onwhich the wiring 2 is formed as described above, a polyimide film 16 isbonded, connecting terminal portions of the wiring 2 are exposed by alaser (FIG. 6b), and the copper foil 1 is etched off (FIG. 6c). As analternative, use of a photosensitive film in place of the polyimide filmmakes it possible to expose connecting terminal portions without using alaser. Subsequently, an LSI chip 3 is mounted on the surface of thepolyimide film 16 on which the wiring pattern is formed. For bonding theLSI chip, a silver paste 4 for semiconductors was used. Next,semiconductor terminal portions and the wiring 2 are connected by wirebonds 100 (FIG. 6d). The thus-formed assembly is loaded in a die fortransfer mold and sealed with a semiconductor-sealing epoxy resin(“CL-7700”, trade name; product of Hitachi Chemical Co., Ltd.) 5 (FIG.6e). Thereafter, solder balls 7 are arranged at the connecting terminalportions and are caused to fuse there (FIG. 6f). The wiring can beconnected to an outer wiring via these solder balls 7.

[0137] With reference to FIG. 7, a description will be given of theseventh embodiment of the present invention.

[0138] A nickel layer of 0.001 mm in thickness (not shown in FIG. 7) isplated on one side of an electrolytic copper foil 1 of 0.035 mm inthickness. Next, a photosensitive dry film resist (“PHOTEC HN340”, tradename; product of Hitachi Chemical Co., Ltd.) is laminated, exposed andthen developed, so that a plating resist for wiring pattern is formed.Subsequently, electrolytic copper plating is conducted in a coppersulfate bath. Applied further are a nickel plating to a thickness of0.003 mm or greater and a gold plating of 99.9% or higher purity to athickness of 0.0003 mm or greater. The plating resist is next strippedoff, whereby a wiring 2 is formed (FIG. 7a). On the copper foil 1 withthe wiring 2 formed thereon as described above, an LSI chip 3 ismounted. For bonding the LSI chip, a silver paste 4 for semiconductorswas used. Next, semiconductor terminal portions and the wiring 2 areconnected by wire bonds 100 (FIG. 7b). The thus-formed assembly isloaded in a die for transfer mold and sealed with asemiconductor-sealing epoxy resin (“CL-7700”, trade name; product ofHitachi Chemical Co., Ltd.) 5 (FIG. 7c). Thereafter, only the copperfoil 1 is dissolved away with an-alkali etchant to expose the nickel.The nickel layer is removed with a nickel stripper having lowcopper-dissolving power so that the wiring portion is exposed (FIG. 7d).Then, a polyimide film 16 with openings made therein as connectingterminal portions is bonded (FIG. 7e). Solder balls 7 are arranged atthe exposed portions of the wiring and are caused to fuse there (FIG.7f). The wiring can be connected to an outer wiring via these solderballs 7.

[0139] With reference to FIG. 8, a description will be given of theeighth embodiment of the present invention.

[0140] On an electrolytic copper foil 1 of 0.035 mm in thickness, aphotosensitive dry film resist (“PHOTEC HN340”, trade name; product ofHitachi Chemical Co., Ltd.) is laminated, exposed and then developed, sothat a plating resist for wiring pattern is formed. Applied further area gold plating of 99.9% or higher purity to a thickness of 0.0003 mm orgreater and a nickel plating to a thickness of 0.003 mm or greater.Further, electrolytic copper plating is conducted in a copper sulfatebath, and the plating resist is stripped off, whereby a wiring 2 isformed (FIG. 8a). To the wiring-formed surface of the copper foil 1 onwhich the wiring pattern 2 is formed as described above, a liquidsealing resin 17 is coated by screen printing, and an insulating layeris formed in such a manner that connecting terminal portions of thewiring 2 are exposed (FIG. 8b). After curing the liquid sealing resin,the copper foil 1 is etched off (FIG. 8c). Subsequently, an LSI chip 3is mounted on the surface of the hardened liquid sealing resin 3 inwhich the wiring pattern exist. For bonding the LSI chip, a silver paste4 for semiconductors was used. Next, semiconductor terminal portions andthe wiring 2 are connected by wire bonds 100 (FIG. 8d). The thus-formedassembly is loaded in a die for transfer mold and sealed with asemiconductor-sealing epoxy resin (“CL-7700”, trade name; product ofHitachi Chemical Co., Ltd.) 5 (FIG. 8e). Thereafter, solder balls 7 arearranged at the connecting terminal portions of the wiring 2 and arecaused to fuse there (FIG. 8f). The wiring can be connected to an outerwiring via these solder balls 7.

[0141] With reference to FIG. 9, a description will be given of theninth embodiment of the present invention.

[0142] A nickel layer of 0.001 mm in thickness (not shown in FIG. 9) isplated on one side of an electrolytic copper foil 1 of 0.035 mm inthickness. Next, a photosensitive dry film resist (“PHOTEC HN340”, tradename; product of Hitachi Chemical Co., Ltd.) is laminated, exposed andthen developed, so that a plating resist for wiring pattern is formed.Subsequently, electrolytic copper plating is conducted in a coppersulfate bath. Applied further are a nickel plating to a thickness of0.003 mm or greater and a gold plating of 99.9% or higher purity to athickness of 0.0003 mm or greater. The plating resist is next strippedoff, whereby a wiring 2 is formed (FIG. 9a). On the copper foil 1 withthe wiring 2 formed thereon as described above, an LSI chip 3 ismounted. For bonding the LSI chip 3, a silver paste 4 for semiconductorswas used. Next, semiconductor terminals and the wiring 2 are connectedby wire bonds 100 (FIG. 9b). The thus-formed assembly is loaded in a diefor transfer mold and sealed with a semiconductor-sealing epoxy resin(“CL-7700”, trade name; product of Hitachi Chemical Co., Ltd.) 5 (FIG.9c). Thereafter, only the copper foil 1 is dissolved away with an alkalietchant to expose the nickel. The nickel layer is removed with a nickelstripper having low copper-dissolving-power so that the wiring portionis exposed (FIG. 9d). Then, a liquid sealing resin 17 is coated byscreen printing, and an insulating layer of the liquid sealing resin 17is formed in such a manner that connecting terminal portions of thewiring 2 are exposed (FIG. 9e). Solder balls 7 are arranged at theconnecting terminal portions of the wiring 2 and are caused to fusethere (FIG. 9f). The wiring can be connected to an outer wiring viathese solder balls 7.

[0143] With reference to FIG. 10, a description will be made about thetenth embodiment of the present invention.

[0144] A nickel layer of 0.001 mm in thickness (not shown in FIG. 10) isplated on one side of an electrolytic copper foil 1 of 0.035 mm inthickness. Next, a photosensitive dry film resist (“PHOTEC HN340”, tradename; product of Hitachi Chemical Co., Ltd.) is laminated, exposed andthen developed, so that a plating resist for a wiring pattern andregistration marks is formed. Subsequently, electrolytic copper platingis conducted in a copper sulfate bath. Applied further are a nickelplating to a thickness of 0.003 mm or greater and a gold plating of99.9% or higher purity to a thickness of 0.0003 mm or greater. Theplating resist is next stripped off, whereby a wiring 2 and registrationmarks 18 are formed (FIG. 10a). Only portions with the registrationmarks 18 formed thereon are held between SUS sheets and then pressed,whereby the registration marks are caused to appear on the back side ofthe copper foil 1 as if they are die-stamped (FIG. 10b). On the copperfoil 1 with the wiring 2 and the registration mark 18 formed thereon asdescribed above, an LSI chip 3 is mounted (FIG. 10c). For bonding theLSI chip 3, a silver paste 4 for semiconductors was used. Next,semiconductor terminals and the wiring 2 are connected by wire bonds 100(FIG. 10d). The thus-formed assembly is loaded in a die for transfermold and sealed with a semiconductor-sealing epoxy resin (“CL-7700”,trade name; product of Hitachi Chemical Co., Ltd.) 5 (FIG. 10e). Aphotosensitive dry film is again laminated on the back side of thecopper foil, and an etching pattern is formed by using the registrationmarks 18. Thereafter, the copper foil 1 and the nickel layer are etchedto form the copper foil 1 into bumps 7 and to expose the wiring portion(FIG. 10f). Subsequently, a solder resist 8 was coated, and aninsulating layer was formed in such a way that the bumps 7 were exposed(FIG. 10g). The wiring pattern can be connected to outer wiring viathese bumps 7.

[0145] With reference to FIG. 11, a description will be given of theeleventh embodiment of the present invention.

[0146] On an electrolytic copper foil 1 of 0.035 mm in thickness, aphotosensitive dry film resist (“PHOTEC HN340”, trade name; product ofHitachi Chemical Co., Ltd.) is laminated, exposed and then developed, sothat a plating resist for plural sets of wiring patterns is formed.Applied further are a gold plating of 99.9% or higher purity to athickness of 0.0003 mm or greater and a nickel plating to a thickness of0.003 mm or greater. Further, electrolytic copper plating is conductedin a copper sulfate bath, and the plating resist is stripped off,whereby plural sets of wiring 2 are formed (FIG. 11a). To thepattern-formed surface of the copper foil 1 with the plural sets ofwiring 2 formed thereon as described above, a polyimide film 19 isbonded, connecting terminal portions of the wiring 2 are exposed by alaser (FIG. 11b), and the copper foil 1 is etched off (FIG. 11c). Afterthe plural sets of wiring 2 are formed on the single polyimide film asdescribed above, LSI chips 3 are mounted. For bonding the LSI chips,die-bonding tapes 4′ for semiconductors were used. Next, semiconductorterminal portions and the wiring 2 are connected by wire bonds 100 (FIG.11d). The thus-formed assembly is loaded in a die for transfer mold andsealed with a semiconductor-sealing epoxy resin (“CL-7700”, trade name;product of Hitachi Chemical Go., Ltd.) 5 (FIG. 11e). Thereafter, solderballs 7 are arranged at the connecting terminal portions of the wiring 2and are caused to fuse there (FIG. 11f). The wiring can be connected toouter wiring via these solder balls 7, respectively. Finally, thepackages connected together with the polyimide film are punched out bydies (FIG. 11g).

[0147] With reference to FIG. 12, a description will be given of thetwelfth embodiment of the present invention.

[0148] An adhesive-coated polyimide film 20 of 0.07 mm in thickness ispunched by dies to form openings at portions where connecting terminalsare to be formed (FIG. 12a). After bonding a copper foil 21 of 0.035 mmin thickness (FIG. 12b), a photosensitive dry film resist (“PHOTECHN340”, trade name; product of Hitachi Chemical Co., Ltd.) is laminated,exposed and then developed, so that an etching resist for plural sets ofwiring patterns is formed. Subsequently, the copper foil is etched andthe resist is stripped off, then plural sets of wiring patterns 2 isformed (FIG. 12c). After the plural sets of wiring patterns are formedon the single polyimide film as described above, LSI chips 3 aremounted. For bonding the LSI chips 3, die-bonding tapes 4′ forsemiconductors were used. Next, semiconductor terminal portions and thewiring 2 are connected by wire bonds 100 (FIG. 12d). The thus-formedassembly is loaded in a die for transfer mold and sealed with asemiconductor-sealing epoxy resin (“CL-7700”, trade name; product ofHitachi Chemical Co., Ltd.) 5 (FIG. 12e). Thereafter, solder balls 7 arearranged at the connecting terminal portions of the wiring and arecaused to fuse there (FIG. 12f). The wiring can be connected to outerwiring via these solder balls 7. Finally, the packages connectedtogether with the polyimide film are punched out by dies (FIG. 12g).

[0149] With reference to FIGS. 13 to 15, a description will be given ofthe thirteenth embodiment of the present invention.

[0150] A nickel layer of 0.001 mm in thickness (not shown in FIG. 13) isplated on one side of an electrolytic copper foil 1 of 0.035 mm inthickness. Next, a photosensitive dry film resist (“PHOTEC HN340”, tradename; product of Hitachi Chemical Co., Ltd.) is laminated, exposed andthen developed, so that a plating resist for plural sets of wiringpatterns is formed. Subsequently, electrolytic copper plating isconducted in a copper sulfate bath. Applied further are a nickel platingto a thickness of 0.003 mm or greater and a gold plating of 99.9% orhigher purity to a thickness of 0.0003 mm or greater. The plating resistis stripped off, whereby wiring 2 are formed (FIG. 13a). Next, thecopper foil 1 with the wiring 2 formed thereon are divided intoindividual units and bonded to a separately-prepared stainless steelframe 22 (thickness: 0.135 mm) via a polyimide adhesive film (FIG. 13b).For the frame, a copper alloy such as phosphor bronze, a copper foil, anickel foil, a nickel alloy foil or the like can also be used. As analternative bonding method, it is possible to use inter alia bondingmaking use of an intermetallic eutectic reaction or bonding making useof an ultrasonic wave. Further, as is depicted in FIG. 14, it is desiredto inspect the wiring on the copper foil 1 beforehand, to select onlyconnection non-defectives 23 and then to bond the thus-selectedconnection non-defectives to the frame 22. In FIG. 14, there are shownthe electrolytic copper foil 1, the frame 22, connection defectives 24,and registration holes 25. Although each cut-off copper foil is providedwith one wiring in this embodiment, plural sets of wiring may bearranged on each cut-off copper foil. As a positional relationshipbetween the frame 22 and each copper foil upon bonding them together,various positional relationships are feasible as shown by way of examplein FIGS. 15(a) and 15(b). FIG. 15 shows the frame 22 in plan view, inwhich there are illustrated an opening 26 in the frame, a mountingposition 27 for the copper foil with the wiring, and a foil-fixingadhesive 28. Next, LSI chips 3 are mounted, and semiconductor terminalportions and their corresponding wiring 2 are connected by wire bonds100 (FIG. 13c). For mounting the LSI chips, die-bonding tapes 4′ forsemiconductors are used. Here, die-bonding silver paste or the like canbe used instead of the bonding tapes 4′. For the mounting ofsemiconductor chips, a conventional wire-bonding method was used. Othermethods such as Flip chips may also be used. The thus-formed assemblywas loaded in a die for transfer mold and sealed with asemiconductor-sealing epoxy resin (“CL-7700”, trade name; product ofHitachi Chemical Co., Ltd.) 5 (FIG. 13d). Thereafter, only the copperfoil 1 was dissolved away with an alkali etchant to expose the nickel.The nickel layer was removed with a nickel stripper having lowcopper-dissolving power so that the wiring portions were exposed. Then,a solder resist 6 was coated and patterned in such a way that connectingterminal portions were exposed. Solder balls 7 were arranged at theexposed portions of the wiring and were caused to fuse there (FIG. 13e).The thus-obtained assembly was cut apart by a cutter and unnecessary cutpieces 101 of the frame 22 were eliminated, so that the assembly wasdivided into individual semiconductor packages (FIG. 13f). Each wiringcan be connected to an outer wiring via its corresponding solder balls7. This embodiment makes it possible to improve the blanking and henceto efficiently fabricate semiconductor packages.

[0151] With reference to FIG. 16, a description will be made about thefourteenth embodiment of the present invention.

[0152] An adhesive-coated polyimide film 29 of 0.07 mm in thickness ispunched by dies to form openings at portions where connecting terminalportions are to be formed. After bonding it to a copper foil of 0.035 mmin thickness, a photosensitive dry film resist (“PHOTEC HN340”, tradename; product of Hitachi Chemical Co., Ltd.) was laminated, exposed andthen developed, so that an etching resist for plural sets of wiringpatterns was formed. Subsequently, the copper foil is etched and theresist is stripped off, whereby plural sets of wiring 2 are formed (FIG.16a). Here, the connecting terminal portions and the wiring 2 can beformed using a material which is formed of a copper foil and a polyimidecoated directly on the copper foil (for example, “50001”, trade name;product of Hitachi Chemical Co., Ltd.). The formation of the openingscan be effected by drilling, laser beam machining such as excimer lasermachining, printing or the like. As a further alternative, they can alsobe formed by using a material, which has been obtained by impartingphotosensitivity to a polyimide, and conducting exposure anddevelopment. Instead of the polyimide, another material such as asealing resin can also be used.

[0153] After forming the plural sets of wiring on the single polyimidefilm as described above, the wiring-formed film was divided into units.They were then bonded to a separately-prepared stainless steel frame 22(thickness: 0.135 mm) via a polyimide adhesive 28 (FIG. 16b). Then, LSIchips 3 were mounted, and semiconductor terminal portions and thecorresponding wiring 2 are connected by wire bonds 100 (FIG. 16c). Forthe mounting of the LSI chips, die-bonding tapes 4′ for semiconductorswere used. The thus-formed assembly was loaded in a die for transfermold and sealed with a semiconductor-sealing epoxy resin (“CL-7700”,trade name; product of Hitachi Chemical Co., Ltd.) 5 (FIG. 16d).Subsequently, solder balls 7 are arranged in the openings, which wereformed in the beginning and are to be converted to connecting terminalportions, and are caused to fuse there (FIG. 16e). The wiring can beconnected to outer wiring via these solder balls 7, respectively.Finally, the packages connected together with the frame are punched outby dies into individual packages (FIG. 16f).

[0154] With reference to FIG. 17, a description will be given of thefifteenth embodiment of the present invention.

[0155] A two-layer flexible base material is composed of a metal foil 31and an insulating base material 32 formed directly thereon (FIG. 17a). Apredetermined resist pattern is formed on the metal foil. By a knownetching process, desired plural sets of wiring patterns 33 are formed,and the resist pattern is then stripped off (FIG. 17b). As the metalfoil, a composite metal foil, which has a thin copper layer on a carrierfoil removable in a subsequent step, or the like can also be usedbesides a single foil such as an electrolytic copper foil, a rolledcopper foil or a copper alloy foil. Specifically, a metal foil—which isobtained by forming a nickel-phosphorus plating layer of 0.2 μm or so inthickness on one side of an electrolytic copper foil of 18 μm inthickness and then plating a thin copper layer to a thickness of 5 μm orso—is applicable. In this case, the thin copper layer is exposed byetching off the copper foil and nickel-phosphorus layer subsequent toformation of a polyimide layer on the thin copper layer. Namely, in thepresent invention, the thin copper layer may be patterned after the thincopper layer is exposed in its entirety, or the carrier foil (copperfoil/thin nickel layer) may be used as a part of a leadframe structure.

[0156] As the insulating base material, on the other hand, a polyimidematerial is ordinary from the viewpoint of process heat resistance andthe like. In this case, it is preferred to use, as the polyimide, apolyimide containing 70 mole % or more of a polyimide having repeatingunits represented by the following formula (1) because a marked warpwould be developed in the base material in a solder reflowing step ifthe polyimide and the copper foil had different coefficients of thermalexpansion:

[0157] Next, holes 34 reaching the copper foil are formed at positionswhich are to be converted to connecting portions to an externalsubstrate in a subsequent step (FIG. 17c). No particular limitation isimposed on the method for the formation of the holes. In addition to alaser beam machining making use of an excimer laser, CO₂ laser or YAGlaser, a wet etching process and so on is applicable.

[0158] A frame base material 37, which is coated with an adhesive 36 andhas been punched out at predetermined portions (openings 35) by punchingor the like, is then bonded to surfaces of the wiring patterns (FIG.17d). In this case, no particular limitation is imposed on the framebase material and a polyimide film or a metal foil such as a copper foilis applicable. If the thickness of the polyimide layer of the two-layerflexible base material is 25 μm and the bonded frame base material is apolyimide film, a film thickness as much as 50 to 70 μm is required toassure sufficient rigidity for the whole frame. Incidentally, noparticular limitation is imposed on the area where the frame basematerial layer is formed. It is also possible to arrange the frame basematerial layer in areas where semiconductor chips are to be mounted.Specifically, where the mounting of chips is effected by thewire-bonding method, the frame base material layer may be arranged inthe entire area insofar as at least terminal portions 38 are exposed forwire-bonding. Semiconductor chips 39 are then mounted, and thesemiconductor chips and the wiring patterns are electrically connectedtogether by gold wires 40 (FIG. 17e). Where a face-down method isadopted as a mounting method for semiconductor chips, on the other hand,the wiring patterns are provided with metal bumps or the like atpredetermined positions (which correspond to the positions of externalconnection electrodes of the semiconductor chips), and the semiconductorchips and the wiring patterns may be electrically connected together viathe-metal bumps. The thus-obtained assembly is then loaded in a die fortransfer mold and is sealed with a resinous sealing material 41 (FIG.17f). In this case, no particular limitation is imposed on the resinoussealing material and, for example, an epoxy resin containing 5 to 80 wt.% of silica of about 10 to 20 μm in diameter can be used. Formed nextare connecting portions 42 which are to be used for establishingconnection with external substrates. As a method for the formation ofthe connecting portions 42, it is possible to apply a method such thatbumps are formed beforehand to a thickness greater than the polyimidefilm by an electrolytic plating process after the step of FIG. 17c orsolder bumps are formed by a solder printing process after sealing withthe resin. Finally, the package portions are cut off from the frame sothat packages are obtained as desired (FIG. 17g).

[0159] The fifteenth embodiment of FIG. 17 will be described morespecifically.

SPECIFIC EXAMPLE 1

[0160] A two-layer flexible base material having an electrolytic copperfoil of 12 μm in thickness on one side thereof (“MCF 5000I”, trade name;product of Hitachi Chemical Co., Ltd.) was provided. A dry film resist(“PHOTEC HK815”, trade name; product of Hitachi Chemical Co., Ltd.) waslaminated on the copper foil and then exposed and developed, whereby adesired resist pattern was obtained. After the copper foil was etchedwith a solution of ferric chloride, the resist pattern was stripped witha solution of potassium hydroxide so that a predetermined wiring patternwas obtained. Using an excimer laser beam machine (“INDEX 200”, tradename; manufactured by Sumitomo Heavy Industries, Ltd.), as many holes asneeded (diameter: 300 μm) were formed at predetermined positions so thatthey extend from a side of an insulating base material and reach a backsurface of the wiring pattern. The following conditions were set for theexcimer laser beam machining—energy density: 250 mJ/cm², reductionratio: 3.0, oscillation frequency: 200 Hz, and illumination pulsenumber: 300 pulses. Prepared next was an adhesive sheet having a 10-μmthick polyimide-base adhesive (“AS 2250”, trade name; product of HitachiChemical Co., Ltd.) on one side of a 50-μm thick polyimide film (“UPILEXS”, trade name; product of Ube Industries, Ltd.). Predetermined areasincluding those corresponding to terminal portions to be used for wirebonding in a subsequent step were removed by punching, and the polyimidefilm and the two-layer flexible base material with the wiring patternformed thereon were subjected to thermocompression via the adhesive. Thefollowing conditions were set for the thermo compressionbonding—pressure: 20 kgf/cm², temperature: 180° C., andthermocompression time: 60 minutes. By electroless nickel and goldplating processes, the terminal portions for the wire bonding were nextapplied with nickel/gold platings. The thicknesses of these platingswere 3 μm and 0.3 μm, respectively. Using a semiconductor-chip-mountingdie-bonding material (“HM-1”, trade name; product of Hitachi ChemicalCo., Ltd.), semiconductor chips were then mounted. The mountingconditions were set as follows—press pressure: 5 kgf/cm², bondingtemperature: 380° C., and compression-bonding time: 5 seconds. Externalelectrode portions of each semiconductor chip were then electricallyconnected with its corresponding wiring pattern by wire bonding. Thethus-obtained assembly was stamped into a leadframe-shaped form, loadedin a die for transfer mold and then sealed at 185° C. for 90 secondswith a semiconductor-sealing epoxy resin (“CL-7700”, trade name; productof Hitachi Chemical Co., Ltd.). The above-mentioned holes were then eachcoated with a predetermined amount of solder by a printing process. Thesolder was caused to fuse in an infrared reflowing oven, so thatexternal connection bumps were formed. Finally, the package portionswere punched out by dies so that packages were obtained as desired.

[0161] With reference to FIG. 18, a description will be made of thesixteenth embodiment of the present invention.

[0162] A two-layer flexible base material is composed of a metal foil 31and an insulating base material 32 formed directly thereon (FIG. 18a). Apredetermined resist pattern is formed on the metal foil. By a knownetching process, desired plural sets of wiring patterns 3 are formed,and the resist pattern is then stripped off (FIG. 18b). As the metalfoil, a composite metal foil, which has a thin copper layer on a carrierfoil removable in a subsequent step, or the like can also be usedbesides a single foil such as an electrolytic copper foil, a rolledcopper foil or a copper alloy foil. Specifically, a metal foil—which isobtained by forming a nickel-phosphorus plating layer of 0.2 μm or so inthickness on one side of an electrolytic copper foil of 18 μm inthickness and then plating a thin copper layer to a thickness of 5 μm orso—is applicable. In this case, the thin copper layer is exposed byetching off the copper foil and nickel-phosphorus layer subsequent toformation of a polyimide layer on the thin copper layer. Namely, in thepresent invention, the thin copper layer may be patterned after the thincopper layer is exposed in its entirety, or the carrier foil (copperfoil/thin nickel layer) may be used as a part of a leadframe structure.As the insulating base material, on the other hand, a polyimide materialis ordinary from the viewpoint of process heat resistance and the like.In this case, it is preferred to use, as the polyimide, a polyimidecontaining 70 mole % or more of a polyimide having repeating unitsrepresented by the formula (1) because a marked warp will be developedin the base material in a solder reflowing step if the polyimide and thecopper foil have different coefficients of thermal expansion.

[0163] Next, holes 34 reaching the copper foil are formed at positionswhich are to be converted to connecting portions to external substratein a subsequent step (FIG. 18c). No particular limitation is imposed onthe method for the formation of the holes. In addition to a laser beammachining making use of an excimer laser, CO₂ laser, or YAG laser, a wetetching process or the like is applicable.

[0164] A frame base material 37, which is coated with an adhesive 36 andhas been punched out at predetermined portions (openings 5) by punchingor the like, is then bonded as a second insulating base material tosurfaces of the wiring patterns (FIG. 18d). If the thickness of thepolyimide layer of the two-layer flexible base material is 25 μm, a filmthickness as much as 50 to 70 μm is required as a thickness of apolyimide film to be bonded in view of a subsequent step in which thepolyimide film is fixed on a frame. Incidentally, no particularlimitation is imposed on the area where the polyimide is bonded. Itsarrangement in areas where semiconductor chips are to be mounted makesit possible to form external connection terminals under thesemiconductor chips like CSPs. Specifically, where the mounting of chipsis effected by the wire-bonding method, the polyimide film may be bondedin the entire area insofar as at least terminal portions 38 are exposedfor wire-bonding. The insulating substrate obtained as described aboveis divided into the individual wiring patterns (FIG. 18e) and are thenfixed on a separately-prepared frame 43 made, for example, of SUS or thelike (FIG. 18f). Semiconductor chips 39 are then mounted, and thesemiconductor chips and the wiring patterns are electrically connectedtogether by gold wires 40 (FIG. 18g). Where a face-down method isadopted as a mounting method of semiconductor chips, on the other hand,the wiring patterns are provided with metal bumps or the like atpredetermined positions (which correspond to the positions of externalconnection electrodes of the semiconductor chips), and the semiconductorchips and the wiring patterns may be electrically connected together viathe metal bumps. The thus-obtained assembly is then loaded in a die fortransfer mold and is sealed with a resinous seating material 41 (FIG.18h). In this cases no particular limitation is imposed on the resinoussealing material and, for example, an epoxy resin containing 5 to 80 wt.% of silica of about 10 to 20 μm in diameter can be used. Formed nextare connecting portions 12 which are to be used for establishingconnection with external substrates. As a method for the formation ofthe connecting portions 12, it is possible to apply a method such thatbumps are formed beforehand to a thickness greater than the polyimidefilm by an electrolytic plating process after the step of FIG. 18c orsolder bumps are formed by a solder printing process after sealing withthe resin. Finally, the package portions are cut off from the frame sothat packages are obtained as desired (FIG. 18i).

[0165] The sixteenth embodiment of FIG. 18 will be described morespecifically.

SPECIFIC EXAMPLE 2

[0166] A two-layer flexible base material having an electrolytic copperfoil of 12 μm in thickness on one side thereof (“MCF 5000I”, trade name;product of Hitachi Chemical Co., Ltd.) was provided. A dry film resist(“PHOTEC HK815”, trade name; product of Hitachi Chemical Co., Ltd.) waslaminated on the copper foil and then exposed and developed, whereby adesired resist pattern was obtained. After the copper foil was etchedwith a solution of ferric chloride, the resist pattern was stripped witha solution of potassium hydroxide so that a predetermined wiring patternwas obtained. Using an excimer laser beam machine (“INDEX 200”, tradename; manufactured by Sumitomo Heavy Industries, Ltd.), as many holes asneeded (diameter: 300 μm) were formed as many as needed at predeterminedpositions so that they extend from a side of an insulating base materialand reach a back surface of the wiring pattern. The following conditionswere set for the excimer laser beam machining—energy density: 250mJ/cm², reduction ratio: 3.0, oscillation frequency: 200 Hz, andillumination pulse number: 300 pulses. Prepared next was an adhesivesheet having a 10-μm thick polyimide-base adhesive (“AS 2250”, tradename; product of Hitachi Chemical Co., Ltd.) on one side of a 50-μmthick polyimide film (“UPILEX S”, trade name; product of Ube Industries,Ltd.). Predetermined areas including those corresponding to terminalportions to be used for wire bonding in a subsequent step were removedby punching, and the polyimide film and the two-layer flexible basematerial with the wiring pattern formed thereon were subjected tothermocompression via the adhesive. The following conditions were setfor the thermo compression bonding—pressure: 20 kgf/cm², temperature:180° C., and thermocompression time: 60 minutes. By electroless nickeland gold plating processes, the terminal portions for the wire bondingwere next applied with nickel/gold platings. The thicknesses of theseplatings were 3 μm and 0.3 μm, respectively. The thus-obtained substratewas divided into the individual wiring patterns and are fixed on aseparately-prepared SUS frame. Using a semiconductor-chip-mountingdie-bonding material (“HM-1”, trade name; product of Hitachi ChemicalCo., Ltd.), semiconductor chips were then mounted. The mountingconditions were set as follows—press pressure: 5 kgf/cm², bondingtemperature: 380° C., and compression-bonding time: 5 seconds. Externalelectrode portions of each semiconductor chip were then electricallyconnected with its corresponding wiring pattern by wire bonding. Thethus-obtained assembly was molded into a leadframe-shaped form, loadedin a die for transfer mold and then sealed at 185° C. for 90 secondswith a semiconductor-sealing epoxy resin (“CL-7700”, trade name; productof Hitachi Chemical Co., Ltd.). The above-mentioned holes were then eachcoated with a predetermined amount of solder by a printing process. Thesolder was caused to fuse in an infrared reflowing oven, so thatexternal connection bumps were formed. Finally, the package portionswere punched out by dies so that packages were obtained as desired.

[0167] With reference to FIGS. 19, 20 and 21, a description will begiven of the seventeenth embodiment of the present invention.

[0168] Plural sets of predetermined wiring patterns 52 are formed on asupporting member 51 (FIG. 19a). As the supporting member, an insulatingbase material such as a polyimide film can be used besides a metal foilsuch as an electrolytic copper foil. When an insulating base material isused, there are two methods. According to the first method,nonthrough-holes reaching the wiring patterns are formed atpredetermined positions of the insulating base material, and externalconnection terminals are formed at exposed portions of the wiringpatterns. The nonthrough-holes can be formed by applying an excimerlaser or a CO₂ laser and so on. According to the second method, adrilled insulating base material provided with an adhesive is formed inadvance and, subsequent to lamination with an electrolytic copper foilor the like, the copper foil is subjected to etching.

[0169] When a metal foil is used, on the other hand, a resist pattern isformed with a photoresist and wiring patterns are then formed byelectroplating while using the metal foil as a cathode. In this case, itis possible to use a conventional electrolytic copper foil and a foilconsisting of an electrolytic copper foil and a thin layer of a metal(nickel, gold, solder or the like) different in chemical etchingconditions from the copper foil provided thereon. Further, copper ispreferred for the wiring patterns. However, when an electrolytic copperfoil is used as a supporting member as mentioned above, it is necessaryto use a metal, which is different in etching conditions from the copperfoil, for the wiring patterns or to form a patterned thin layer, whichwill serve as a barrier layer upon etching the copper foil, beforeapplication of a patterned copper plating.

[0170] Next, after semiconductor devices 54 are mounted by die-bondingmaterials 53, terminals of the semiconductor devices and wiring patternsare electrically connected (FIG. 19b), and plural sets of thesemiconductor devices and wiring patterns are all together sealed with aresinous sealing material 56 by the transfer molding process (FIG. 19c).No particular limitation is imposed on the resinous sealing materialand, for example, an epoxy resin containing 5 to 80 wt. % of silica ofabout 10 to 20 μm in diameter can be used. The present invention is notlimited to cases making use of a face-up method as a mounting method forsemiconductor devices but is also applicable to cases making use of aface-down method. Specifically, it is only necessary to form bumps forface-down bonding at predetermined positions on the wiring patterns 52by a plating process or the like and then to electrically connectexternal connecting portions of the semiconductor devices with thebumps. Further, it is effective to make to packages easy to divide in asubsequent step as shown in FIG. 20 and FIG. 21. Of these, FIG. 20 showsgrooves 59 formed in boundary portions between individual packageportions. The width, depth and the like of each groove can be modifieddepending on the dimensions which the die for transfer mold can receivefor processing. Further, FIG. 21 illustrates a transfer molding processwhich is carried out using a grid-shaped intermediate plate 60 hollowedout beforehand at areas corresponding to the individual packageportions. Where the supporting member is a metal foil, the supportingmember is removed by a chemical etching process and external connectionterminals 57 are formed at predetermined positions (FIG. 19d). When aninsulating base material is used as a supporting member, it is onlynecessary to selectively remove the insulating base material atpredetermined areas by a laser or the like. Finally, the substrate whichhas been sealed as a whole is cut apart into unit portions 58.Incidentally, a solder resist layer may be formed on exposed surfaces ofthe wiring patterns for protecting the wiring patterns.

[0171] The seventeenth embodiment will be described specifically.

SPECIFIC EXAMPLE 3

[0172] On a shiny surface of an electrolytic copper foil of 35 μm inthickness and 250 mm squares in external shape, a photosensitive dryfilm resist (“PHOTEC HN640”, trade name; product of Hitachi ChemicalCo., Ltd.) was laminated, followed by exposure and development so that adesired resist pattern (minimum line/space=50 μm/50 μm) was formed. Asmany as 300 (4 blocks/250 mm squares, 75 patterns/block) identicalwiring patterns which were each consisted of 0.2 μm thick nickel, 30 μmthick copper, 5 μm thick nickel and 1 μm thick soft gold were nextformed by an electroplating method. The resist pattern was next strippedoff using a 3 wt. % solution of potassium hydroxide of 35° C. Theresultant assembly was dried at 85° C. for 15 minutes and then cut intothe individual blocks. Using a semiconductor-device-mounting die-bondingmaterial (“HM-1”, trade name; product of Hitachi Chemical Co., Ltd.),semiconductor devices were then bonded. The bonding conditions were setas follows—press pressure: 5 kg/cm², temperature: 380° C., andcompression-bonding time: 5 seconds. External terminals of eachsemiconductor device were then electrically connected with itscorresponding gold-plated terminal portions (second connecting portions)by wire bonding. The thus-obtained assembly was loaded in a die fortransfer mold. Using a semiconductor-sealing epoxy resin (“CL-7700”,trade name; product of Hitachi Chemical Co., Ltd.), the 75 wiringpatterns (corresponding to 1 block) were sealed all together at 185° C.for 90 seconds so that the individual wiring patterns were transferredinto the sealing material. Next, the electrolytic copper foil was etchedoff at desired portions with an alkali etchant (“A Process”, trade name;product of Japan Meltex, Inc.). The temperature and spraying pressure ofthe etching solution were 40° C. and 1.2 kgf/cm², respectively. Solderpatterns were then formed at external connection terminal portions by aprinting process. The solder was caused to fuse in an infrared reflowingoven, so that external connection bumps were formed. Finally, theassembly was divided into individual package portions by a diamondcutter so that packages were obtained as desired.

SPECIFIC EXAMPLE 4

[0173] On a shiny surface of an electrolytic copper foil of 35 μm inthickness and 250 mm squares in external shape, a photosensitive dryfilm resist (“PHOTEC HN640”, trade name; product of Hitachi ChemicalCo., Ltd.) was laminated, followed by exposure and development so that adesired resist pattern (minimum line/space=50 μm/50 μm). As many as 300(4 blocks/250 mm squares, 75 patterns/block) identical wiring patternswhich were each consisted of 0.2 μm thick nickel, 30 μm thick copper, 5μm thick nickel and 1 μm thick soft gold were next formed by anelectroplating method. The resist pattern was next stripped off using a3 wt. % solution of potassium hydroxide of 35° C. The resultant assemblywas dried at 85° C. for 15 minutes and then cut into the individualblocks. Using a semiconductor-device-mounting die-bonding material(“HM-1”, trade name; product of Hitachi Chemical Co., Ltd.), thesemiconductor devices were then bonded. The bonding conditions were setas follows—press pressure: 5 kg/cm², temperature: 380° C., andcompression-bonding time: 5 seconds. External terminals of eachsemiconductor device were then electrically connected with itscorresponding gold-plated terminal portions (second connecting portions)by wire bonding. Using as an intermediate plate a grid-shaped stainlesssteel plate hollowed out at areas corresponding to individual packageareas, the thus-obtained assembly was loaded in a die for transfer mold.Using a semiconductor-sealing epoxy resin (“CL-7700”, trade name;product of Hitachi Chemical Co., Ltd.), the 75 wiring patterns(corresponding to 1 block) were sealed all together at 185° C. for 90seconds so that the individual wiring patterns were transferred into thesealing material. A grid portion of the intermediate plate was taperedat 12° to facilitate separation of the individual packages from theintermediate plate. Next, the electrolytic copper foil was etched off atdesired portions with an alkali etchant (“A Process”, trade name;product of Japan Meltex, Inc.). Each package portion is held in place bythe grid-shaped intermediate plate. The temperature and sprayingpressure of the etching solution were 40° C. and 1.2 kgf/cm²,respectively. Finally, solder patterns were formed at externalconnection terminal portions by a printing process. The solder wascaused to fuse in an infrared reflowing oven, so that externalconnection bumps were formed. Individual package portions were separatedfrom the intermediate plate so that packages were obtained as desired.

[0174] With reference to FIG. 22, a description will be given of theeighteenth embodiment of the present invention.

[0175] Plural sets of predetermined resist patterns 62 (FIG. 22b) areformed on an electrically-conductive temporary supporting member 61(FIG. 22a). Next, wiring patterns 63 are formed at exposed portions ofthe temporary supporting member by an electroplating process. In thiscase, no particular limitation is imposed on the temporary supportingmember. For example, it is possible to use a conventional electrolyticcopper foil and a foil consisting of an electrolytic copper foil and athin layer of a metal (nickel, gold, solder or the like) different inchemical etching conditions from the copper foil provided thereon.Further, copper is preferred for the wiring patterns. However, when anelectrolytic copper foil is used as a temporary supporting member asmentioned above, it is necessary to use a metal, which is different inetching conditions from the copper foil, for the wiring patterns or toform a patterned thin layer, which will serve as a barrier layer uponetching the copper foil, before application of a patterned copperplating. No particular limitation is imposed on the thickness of thetemporary supporting member insofar as no inconvenience or problemarises in-matters such as the handling in subsequent steps and thedimensional stability upon packaging semiconductor devices. After aplating (usually, nickel/gold) 64 which is to be used for gold wirebonding is applied using the temporary supporting member as a cathode,the resist pattern is removed (FIG. 22c). The present invention is notlimited to cases making use of a face-up method as a mounting method forsemiconductor devices but is also applicable to cases making use of aface-down method for example. Specifically, it is only necessary to formbumps for face-down bonding at predetermined positions on the wiringpatterns 63 by a plating process or the like and then to electricallyconnect external connecting portions of the semiconductor devices withthe bumps.

[0176] Next, after semiconductor devices 65 are bonded by die-bondingmaterials 66, external connection terminals of the semiconductor devicesand their corresponding wiring patterns are electrically connected (FIG.22d). The resultant assembly is then loaded in a die for transfer moldand is sealed with a resinous sealing material 68 (FIG. 22e). In thiscase, no particular limitation is imposed on the resinous sealingmaterial and, for example, an epoxy resin containing 5 to 80 wt. % ofsilica of about 10 to 20 μm in diameter can be used.

[0177] Then, predetermined metal patterns 69 are formed at positionscorresponding to the external connection terminals (FIG. 22f). In thiscase, any metal can be used insofar as it is not etched under conditionsfor etching off the electrically-conductive temporary supporting member.For example, solder, gold, nickel/gold or the like can be used. As aprocess for the formation of the metal patterns, a known electroplatingprocess or solder printing process can be applied. Further, when formingsolder patterns as the metal patterns 69 by a printing process, solderbumps 70 can be formed by reflowing. In this case, by adjusting thethickness of the patterns 69, it is possible to control the height ofthe reflowed solder bumps 70. The temporary supporting member is nextremoved at predetermined portions while using the metal patterns as anetching resist, whereby the wiring patterns are exposed. Finally, theassembly is divided into individual packages 71 by stamping or dicing(FIG. 22g). Incidentally, where the exposed wiring patterns are notprotected by a corrosion-resistant metal such as nickel, areas otherthan the external connection terminal portions may be coated with aknown solder resist or the like. When using solder as metal patterns, noparticular limitation is imposed. on the reflowing step. The reflowingstep can be performed either before or after dividing the assembly intothe individual packages. As a further alternative, the reflowing stepcan also be conducted before mounting the individual packages onexternal wiring boards.

[0178] The eighteenth embodiment will be described specifically.

SPECIFIC EXAMPLE 5

[0179] On a shiny surface of an electrolytic copper foil of 70 μm inthickness, a photosensitive dry film resist (“PHOTEC HN640”, trade name;product of Hitachi Chemical Co., Ltd.) was laminated, followed byexposure and development so that a desired resist pattern (minimumline/space=50 μm/50 μm) was formed. Wiring patterns which were eachconsisted of 0.21 μm thick nickel, 30 μm thick copper, 51 μm thicknickel and 1 μm thick soft gold were next formed by an electroplatingmethod. The resist pattern was next stripped off using a 3 wt. %solution of potassium hydroxide of 35° C. After the resultant assemblywas dried at 85° C. for 15 minutes, semiconductor devices were bondedusing a semiconductor-device-mounting die-bonding material (“HM-1”,trade name; product of Hitachi Chemical Co., Ltd.). The bondingconditions were set as follows—press pressure: 5 kg/cm², temperature:380° C., and compression-bonding time: 5 seconds. External terminals ofeach semiconductor device were then electrically connected with itscorresponding gold-plated terminal portions (second connecting portions)by wire bonding. The thus-obtained assembly was loaded in a die fortransfer mold. Using a semiconductor-sealing epoxy resin (“CL-7700”,trade name; product of Hitachi Chemical Co., Ltd.), the assembly wassealed at 185° C. for 90 seconds so that the wiring patterns weretransferred into the sealing material. Next, a photosensitive dry filmresist (“PHOTEC HN340”, trade name; product of Hitachi Chemical Co.,Ltd.) was laminated on an electrolytic copper foil, followed by exposureand development so that a desired resist pattern was formed. A 40 μmthick solder pad (diameter: 0.3 mm, arrangement pitch: 1.0 mm) wasformed by an electroplating method. Next, after the dry film resist wasstripped off, the electroplated copper foil was etched off at desiredportions with an alkali etchant (“A Process”, trade name; product ofJapan Meltex, Inc.). The temperature and spraying pressure of theetching solution were 40° C. and 1.2 kgf/cm², respectively. Finally, thesolder was caused to fuse in an infrared reflowing oven, so thatexternal connection bumps were formed.

[0180] With reference to FIGS. 23, 24 and 25, a description will begiven of the nineteenth embodiment of the present invention.

[0181] The construction of a semiconductor mounting frame will bedescribed with reference to FIG. 23. Numeral 89 indicatessemiconductor-mounting substrates, each of which consisted of aninsulating base material and wiring. Plural substrates are connectedtogether via connecting portions 90. Each connecting portion 90 isprovided with pinholes 91 as reference positions. Recognition marksemployed in image recognition may be used in place of the pinholes 91.Based on these reference positions, positioning is performed insubsequent steps. Especially upon molding semiconductors with resin,positional registration is effected by inserting pins, which arearranged inside a cavity, in the pinholes 91.

[0182] Referring to FIGS. 24 and 25, a further description will begiven. A nickel layer of 0.001 mm in thickness (not shown in FIGS. 24and 25) was formed by an electrolytic plating process on one side of anelectrolytic copper foil 81 of about 0.070 mm in thickness which is anelectrically-conductive temporary substrate. Next, a photosensitivedry-film resist (“PHOTEC HN340”, trade name; product of Hitachi ChemicalCo., Ltd.) was laminated, followed by exposure and development so that aplating resist for plural sets of wiring patterns was formed. Theintensity of the exposure at this time is 70 mJ/cm². Further,electrolytic copper plating is conducted in a known copper sulfate bathand the resist is stripped off, whereby plural sets of wiring 82 areformed (FIG. 24a, FIG. 25a). Here, as is illustrated in FIG. 25a, it maybe contemplated to form plated copper 82′ at the connecting portionstoo. This makes it possible to provide the resulting frame with stillenhanced rigidity. Each of the constructions shown in FIG. 24a and FIG.25a can also be obtained by providing beforehand a base materialcomposed of three layers of copper/thin nickel layer/copper and formingone of the copper foils into wiring in a usual etching step. Further,the construction of the copper foil 81/thin nickel layer (notshown)/copper wirings 82 (and 82′) obtained here may be replaced by atwo-layer structure free of the thin nickel layer, such as copperfoil/nickel wirings, nickel foil/copper wirings, or the like. Althoughthe selectable kinds of metals are not limited to those of the presentembodiment, it is a preferred standard for the selection to allowwirings to selectively remain when some parts of the temporary substrateare etched off in a subsequent step (FIG. 24c, FIG. 25c). As theelectrically-conductive temporary substrate becomes a material whichmakes up the connecting portions of the frame, a greater thickness ispreferred. There is however a subsequent step to etch it-off partly, sothat it is necessary to select an appropriate thickness. The thicknessof the electrically-conductive temporary substrate varies depending onthe material. For example, when a copper foil is used, about 0.03 to 0.3mm or so is preferred. A polyimide adhesive 83 is next applied to thewiring-containing surface of the copper foil 81 with the plural sets ofwiring 82 formed thereon. Here, the polyimide adhesive 83 is not limitedto this material. It is possible to use, for example, an epoxy adhesivefilm, a film formed of a polyimide film and an adhesive coated thereon,or the like. Next, holes 84 for the external connection terminals areformed using an excimer laser (FIG. 24b, FIG. 25b). For the sake ofsimplification of subsequent steps, it is suited to arrange connectingterminals before mounting semiconductors. As another method for theformation of these holes 84, it is possible to form beforehand the holes84 for the external connection terminals in a film by drilling orpunching and then to bond the film so formed. Although no problem orinconvenience would arise even if a metal to be employed as theconnecting terminals (which are designated at numeral 88 in FIG. 24f andFIG. 25f), such as a solder or the like, is filled at this stage, theresulting metal bumps may become an obstacle in the subsequentsemiconductor mounting step and resin sealing step. Thus, it ispreferred to form a metal at a subsequent step. It is preferred tolocate the holes for the external connection terminals (or terminals) inthe mounting substrate portions for the semiconductor devices, in theform of-arrays on the side opposite to the side on which thesemiconductor devices are mounted.

[0183] Next, a portion of the electrolytic copper foil as the temporarysubstrate, the portion being the area where the wiring patters areformed, was etched off. As this etching solution, it is preferred tochoose an etching solution and etching conditions, which in the case ofthis embodiment, provide a substantially higher dissolution velocity forcopper than for nickel. Employed in this embodiment are an alkalietchant (“A Process”, trade name; product of Japan Meltex Inc.) as anetching solution and, for example, a solution temperature of 40° C. anda spray pressure of 1.2 kgf/cm². It is to be noted that the kind ofsolution and the conditions specified here are merely illustrative. Bythis step, the thin nickel layer in the substrate is exposed. Uponetching only this thin nickel layer, it is preferred to choose anetching solution and etching conditions so that a substantially higherdissolution velocity is provided for nickel than for copper. In thisembodiment, selective etching was conducted with a nickel etchant(“Melstrip N950”, trade name; product of Japan Meltex, Inc.). Thetemperature and spraying pressure of the etching solution were set at40° C. and 1.2 kgf/cm², respectively. It is to be noted that the kind ofthe solution and conditions specified here are merely illustrative.Through these steps, the temporary substrate is allowed to remain as theconnecting portions, whereby a semiconductor mounting frame havingrigidity is obtained (FIG. 24c, FIG. 25c). In this embodiment,electroless nickel-gold plating is applied to terminal portions of thecopper wirings on this frame (not shown). This is needed forwire-bonding chips in a subsequent step. Such surface treatment can beapplied as needed.

[0184] Semiconductor chips 85 are then mounted. For bonding thesemiconductor chips, semiconductor die-bonding tapes 86 (for example,“HM-1”, trade name; product of Hitachi Chemical Co., Ltd.) were used. Ifthere is no wiring under the chips, the chips may be bonded using adie-bonding silver paste. Next, terminal portions of the semiconductorsand the wiring are connected by wire bonds 100 (FIG. 24d, FIG. 25d). Theconnection with the terminals of the semiconductors can be effected byanother method, for example, by face-down connection making use of Flipchips or by bonding making use of an anisotropic conductive adhesive.The assembly so formed is loaded in a die for transfer mold and issealed using a semiconductor-sealing epoxy resin (“CL-7700”, trade name;product of Hitachi Chemical Co., Ltd.) 87 (FIG. 24e, FIG. 25e).Thereafter, solder balls 88 are arranged in the connecting holes formedat connecting terminal portions of the wiring 82 and are then caused tofuse (FIG. 24f, FIG. 25f). These solder balls 88 become so-calledexternal connection terminals. The plural semiconductor devicesconnected together by the connecting portions 102 are punched by dies,so that the individual semiconductor devices are obtained (FIG. 24g,FIG. 25g).

[0185] In this embodiment, the semiconductor mounting frame andsemiconductor device fabrication process make it possible to obtain aframe having sufficient rigidity in the fabrication of semiconductordevices, such as BGAs, CSPs or the like, by using a film-shapedsubstrate such as a polyimide tape and so on. By using this frame,semiconductor devices can be fabricated with high accuracy andefficiency.

[0186] Owing to the present invention, semiconductor packages capable ofmeeting the move toward higher integration of semiconductor chips can befabricated stably with good productivity.

1. A process for the fabrication of a semiconductor package, whichcomprises the following steps: 1A) forming wiring on one side of aconductive temporary supporting member; 1B) mounting a semiconductordevice on said conductive temporary supporting member on which saidwiring has been formed, and then electrically connecting a terminal ofsaid semiconductor device with said wiring; 1C) sealing saidsemiconductor device with resin; 1D) removing said conductive temporarysupporting member to expose said wiring; 1E) forming an insulating layerover said exposed wiring pattern at an area other than position where anexternal connection terminal is to be formed; and 1F) forming saidexternal connection terminals on said wiring pattern at said positionswhere said insulating layer has not been formed.
 2. A process for thefabrication of a semiconductor package, which comprises the followingsteps: 2A) forming wiring on one side of a conductive temporarysupporting member; 2B) forming an insulating supporting member over saidone side of said conductive temporary supporting member, said one sidecarrying said wiring formed thereon; 2C) removing said conductivetemporary supporting member to transfer said wiring pattern onto saidinsulating supporting member; 2D) removing said insulating supportingmember at positions where an external connection terminal is to beformed for said wiring pattern, whereby a through-holes is formed forsaid external connection terminal; 2E) mounting a semiconductor deviceon said insulating supporting member on which said wiring has beentransferred, and then electrically connecting a terminal of saidsemiconductor device with said wiring; 2F) sealing said semiconductordevice with resin; and 2G) forming, in said through-hole for saidexternal connecting terminal, said external connection terminal so thatsaid external connection terminal is electrically connected to saidwiring.
 3. A process for the fabrication of a semiconductor package,which comprises the following steps: 3A) forming wiring on one side of aconductive temporary supporting member; 3B) mounting a semiconductordevice on said conductive temporary supporting member on which saidwiring has been formed, and then electrically connecting a terminal ofsaid semiconductor device with said wiring; 3C) sealing saidsemiconductor device with resin; 3D) removing said conductive temporarysupporting member at an area other than position where an externalconnection terminal for said wiring is to be formed, whereby saidexternal connection terminal made from said conductive temporarysupporting member are formed; and 3E) forming an insulating layer atsaid area other than said position of said external connection terminal.4. A process for the fabrication of a semiconductor package, whichcomprises the following steps: 4A) forming an wiring on one side of aconductive temporary supporting member; 4B) mounting a semiconductordevice on said conductive temporary supporting member on which saidwiring has been formed, and then electrically connecting a terminal ofsaid semiconductor device with said wiring; 4C) sealing saidsemiconductor device with resin; 4D) forming a metal pattern, which isdifferent in conditions for removal from said conductive temporarysupporting member, on another side of said conductive temporarysupporting member, said another side being opposite to said one sidewhere said semiconductor device has been mounted, at a position where anexternal connection terminal for said wiring patterns is to be formed;and 4E) removing said conductive temporary supporting member at an areaother than said position where said metal pattern has been formed.
 5. Aprocess for the fabrication of semiconductor packages, which comprisesthe following steps: 5A) forming plural sets of wiring on one side of aninsulating supporting member; 5B) removing said insulating supportingmember at positions where external connection terminals for said wiringare to be formed, whereby through-holes for said external connectionterminals are provided; 5C) mounting semiconductor devices on saidinsulating supporting member on which said plural sets of wiring havebeen formed, and then electrically connecting terminals of saidsemiconductor devices with said wiring, respectively; 5D) sealing saidsemiconductor devices with resin; 5E) forming, in said through-holes forsaid external connection terminals, said external connection terminalsso that said external connection terminals are electrically connected tosaid wiring; and 5F) separating the resultant assembly into individualsemiconductor packages.
 6. A process for the fabrication ofsemiconductor packages, which comprises the following steps: 6A) formingplural sets of wiring on one side of a conductive temporary supportingmember; 6B) cutting apart said conductive temporary substrate so thatsaid plural sets of wiring formed on said conductive temporarysupporting member are divided to include a predetermined number ofwiring per unit, and then fixing on a frame said separated conductivetemporary supporting member with said wiring formed thereon; 6C)mounting semiconductor devices on said conductive temporary substrateson which said wiring have been formed, and then electrically connectingterminals of said semiconductor devices with said wiring, respectively;6D) sealing said semiconductor devices with resin; 6E) removing saidconductive temporary substrate to expose said wiring; 6F) forming aninsulating layer over said exposed wiring patterns at areas other thanpositions where external connection terminals are to be formed; 6G)forming said external connection terminals at said positions where saidinsulating layer for the wiring has not been formed; and 6H) separatingthe resultant assembly into individual semiconductor packages.
 7. Aprocess for the fabrication of semiconductor packages, which comprisesthe following steps: 7A) forming plural sets of wiring on one side of aninsulating supporting member; 7B) removing said insulating supportingmember at positions where external connection terminals for said wiringare to be formed, whereby through-holes for said external connectionterminals are provided; 7C) cutting apart said insulating supportingmember so that said plural sets of wiring formed on said insulatingsupporting member are divided to include a predetermined number ofwiring per unit, and then fixing on a frame said separated insulatingsupporting member with said wiring formed thereon; 7D) mountingsemiconductor devices on said insulating supporting members on whichsaid wiring have been formed, and then electrically connecting terminalsof said semiconductor devices with said wiring, respectively; 7E)sealing said semiconductor devices with resin; 7F) forming, in saidthrough-holes for said external connection terminals, said externalconnection terminals so that said external connection terminals areelectrically connected to said wiring; and 7G) separating the resultantassembly into individual semiconductor packages.
 8. A process for thefabrication of a semiconductor package provided with a single layer ofwiring, one side of said wiring having a first connecting function ofbeing connected with a semiconductor device and an opposite side of saidwiring having a second connecting function of being to be connected toexternal wiring, which comprises the following steps 8A, 8B, 8C and 8D:8A) working a heat-resistant insulating base material having a metalfoil, thereby forming said metal foil into plural sets of wiringpatterns; 8B) forming a hole at a position, for exhibiting said secondconnecting function which is to be formed in a subsequent step, so thatsaid hole extends from a side-of said insulating base material to saidwiring patterns; 8C) bonding a frame base material, which makes anopening through a predetermined portion thereof, to desired position ona surface of said wiring patterns and a surface of said insulating basematerial, the latter surface being located adjacent to said wiringpatterns, respectively; and 8D) mounting said semiconductor device,electrically connecting a terminal of said semiconductor device withsaid wiring pattern, and then sealing said semiconductor device withresin.
 9. A process for the fabrication of semiconductor packagesprovided with a single layer of wiring, one side of said wiring having afirst connecting function of being connected with a semiconductor deviceand an opposite side of said wiring having a second connecting functionof being connected to external wiring, which comprises the followingsteps 9A, 9B, 9C and 9D: 9A) working a heat-resistant insulating basematerial having a metal foil, thereby forming said metal foil intoplural sets of wiring patterns; 9B) forming a hole at a position forexhibiting said second connecting function which is to be formed in asubsequent step, so that said hole extend from a side of said insulatingbase material to said wiring patterns; 9C) bonding a second insulatingbase material, which makes an opening through a predetermined portionthereof, to a desired position on a surface of said wiring patterns anda surface of said insulating base material, the latter surface beinglocated adjacent to said wiring patterns, respectively, whereby aninsulating supporting member is formed; 9D) cutting apart saidinsulating supporting member so that said plural sets of wiring formedon said insulating supporting member are divided to include apredetermined number of wiring per unit, and then fixing on a frame saidseparated insulating supporting member with said wiring formed thereon;and 9E) mounting said semiconductor device, connecting a terminal ofsaid semiconductor device with said wiring, and then sealing saidsemiconductor device with resin.
 10. A process for the fabrication ofsemiconductor packages, which comprises the following steps: 10A)forming plural sets of wiring on one side of a supporting member; 10B)mounting plural semiconductor devices on said supporting member on whichsaid wiring have been formed, and then electrically connecting terminalsof said semiconductor devices with said wiring; 10C) subjecting saidplural sets of electrically-connected semiconductor device and wiring togang sealing with resin; 10D) removing desired portions of saidsupporting member to-expose predetermined portions of said wiring, andforming external connection terminals so that said external connectionterminals are electrically connected to said exposed wiring; and 10E)separating the resultant assembly into individual semiconductorpackages.
 11. The fabrication process of semiconductor packagesaccording to any one of claims 1 to 10, wherein subsequent to thesealing of said semiconductor device or devices with said resin, ahardened product of said sealing resin is subjected to heat treatment.12. A semiconductor package fabricated by the process according to anyone of claims 1 to
 11. 13. A process for the fabrication of asemiconductor device packaging frame, said frame being provided withplural semiconductor-device-mounting portions, portions connectingtogether said plural semiconductor-device-mounting portions, and aregistration mark portion, which comprises the following steps: (a)forming wiring for said semiconductor-device-mounting portions on aconductive temporary substrate, (b) transferring said wiring onto aresin substrate, and (c) etching off said conductive temporarysubstrate; wherein upon etching off said conductive temporary substratein step (c), said conductive temporary substrate partly remains to formsome of said connecting portions.